U.S. Pat. No. 5,761,121 discloses an example of a PMOS non-volatile, programmable and electrically erasable memory. The structure of this type of memory is well known to persons skilled in the art. More precisely, this type of cell includes a floating gate transistor and a control gate made by implantation within a semiconductor substrate. This buried layer that acts as a control gate is capacitively coupled to the floating gate. The control gate and the floating gate transistor are electrically isolated by an isolation area, for example of the STI (Shallow Trench Isolation) type.
The layer of gate material, usually polysilicon, within which the transistor floating gate is made, is isolated from the active area by a dielectric, for example made of silicon dioxide. It has been observed that it is advisable to use a dielectric not more than 60 Å thick so as to achieve good data retention. It has been observed that the gate dielectric is thinner at the interface between the isolation area, for example of the STI type, and the gate material. The result is then a data retention problem.